A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in the sensor pixels. After the integration cycle is completed, charge is converted into a voltage that is supplied to the output terminals of the sensor. The charge to voltage conversion is accomplished either directly in the sensor pixels, such as in the Active Pixel CMOS image sensors, or remotely off the sensing area, in charge conversion amplifiers. The key element of every charge conversion amplifier is the charge detection node. As charge is transferred onto the node, its potential changes in proportion to the amount of transferred charge and this represents the signal. The charge detection node is typically connected to a gate of a suitable MOS transistor that serves as the first stage of the amplifier. The charge detection node is also provided with a reset means that removes charge from the node after sensing.
There are many charge detection node and amplifier designs known in the literature. The most popular structure is the Floating Diffusion (FD) architecture. The detail description of such systems can be found, for example, in the book: “Solid-State Imaging with Charge-Coupled Devices” by Albert J. P. Theuwissen pp. 76–79 that was published in 1995 by Kluwer Academic Publishers.
Another type of charge detection concept is based on the Floating Gate (FG) architecture. The relatively recent description of this concept has appeared in the article: “Low-Noise and High-Speed Charge Detection in High-resolution CCD Image Sensors” by Hynecek, published in IEEE Transactions on Electron Devices vol. 44 No. 10 Oct. 1997. However, the most promising design of the charge detection system, that has high performance and is very compact, is the BCD charge detection amplifier described in U.S. Pat. No. 5,546,438 to Hynecek. In this system, charge that moves in the bulk of the semiconductor in a CCD channel modulates the threshold of a transistor that overlies the channel.
The performance of each charge detection system can be compared and evaluated according to the following main criteria: the charge conversion factor, dynamic range, noise, reset feed-through, and linearity. The charge conversion factor is determined by the over all detection node capacitance that also includes the node parasitic capacitances. It is thus desirable to minimize the parasitic capacitances and maximize the charge conversion factor. The Dynamic Range (DR) of the node is determined by the ratio of maximum charge handling capacity to the noise floor. It is desirable to minimize the noise floor in order to maximize the DR.
All the known charge detection readout concepts can be divided into two categories: the charge detection readouts that sense charge destructively and the nondestructive charge readouts. The destructive charge readout nodes typically reset charge to a predetermined reference level, which causes generation of kTC noise. kTC noise may be removed from the signal later by a complicated CDS signal processing method. The non-destructive charge readouts, on the other hand, remove all charge from the node thus resetting the node to zero and avoiding the generation of kTC noise. The nondestructive charge readout is preferable in high-speed applications, since this simplifies the signal processing, which ultimately leads to a superior performance.
An example of the nondestructive charge readout is the BCD concept illustrated in FIG. 1. In this structure the charge detection node is integrated together with the first stage amplifier transistor to a single compact device. This eliminates many parasitic capacitances that would normally result from interconnects between the node, the reset means, and the amplifier input transistor. Another advantage of this structure is its low reset feed through. This is due to the fact that the reset gate couples strongly only to the MOS transistor gate that is bypassed to ground.
However, the BCD charge detection system has also some disadvantages. The main problem is the low conversion gain described by the formula Gc=q/(2*Cg). The factor 2 appearing in the denominator significantly reduces the conversion gain and makes it less competitive with more conventional structures. The second significant problem is the current carrying capacity of the overlying MOS transistor. The current is limited by a complicated channel potential profile design and cannot be sufficiently increased to lower the transistor Johnson noise. This problem increases the amplifier noise floor and limits the detection of low-level signals. The third problem of the BCD designs is its DR. The complicated channel potential profile also limits the amount of charge that can be handled by the structure, which in turn limits the available output voltage swing. The BCD detector also exhibits some non-linearity in charge to voltage transfer characteristic, however, this does not seem to be very important in systems where the output signal is digitized and processed using DSP techniques.